1. Technical Field
The present invention relates generally to memory transactions and, more particularly, to an opaque memory region for a PCI bridge.
2. Related Art
Transparent peripheral component interconnect (PCI) bridges or transparent peripheral component interconnect extended (PCIx) bridges (cumulatively referred to herein as “transparent PCI/PCIx bridges”) are often used within a computer system to provide electrical isolation or to segregate devices based on speed, bus width or other characteristics. The requirements and features specified for a transparent PCI/PCIx bridges are set out in the PCI Special Interest Group, PCI Local Bus Specification, Revision 2.2, Dec. 18, 1998; PCI Special Interest Group, PCI-to-PCI Bridge Architecture Specification, Revision 1.1, Dec. 18, 1998; and the PCI Special Interest Group, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, Jul. 24, 2000 (hereinafter cumulatively referred to as “the PCI Specifications”). One characteristic of a PCI/PCIx based computer system is that it regards all system memory as a single memory address space, i.e., it looks at all system memory resources as a single entity despite their distributed nature. The single memory address space is shared by the host complex and all memory mapped I/O devices.
Referring to FIG. 1, forwarding of memory transactions 2 between a primary bus 4 and a secondary bus 6 by a transparent PCI/PCIxbridge is shown. A “primary bus” is the PCI interface that is connected to the PCI bus closest to the host CPU, and a “secondary bus” is the PCI interface that is connected to the PCI bus farthest from the host CPU. In order to maintain the integrity of the single memory address space 10, each transparent PCI/PCIx bridge is required to reserve (or allocate) a memory address range 12 of space 10 for a respective I/O device. (The PCI Specifications allow a bridge to claim two separate memory address ranges—prefetchable and non-prefetchable—but only one is illustrated in FIG. 1. Each memory address range allowed by the PCI Specifications is transparent and function as illustrated in FIG. 1.) Memory address range 12 reserved by the bridge may be specified by the contents of the bridge's memory base address register and its memory limit address register. Memory transactions 2 that are claimed by the bridge, and target range 12, must be logically unaffected by the bridge regardless of whether the transactions are initiated on the primary 4 or secondary bus 6. As shown, a memory transaction 2A initiated on primary bus 4 of the bridge (left side of FIG. 1) is claimed and passed through to secondary bus 6 of the bridge (right side of FIG. 1) if it falls within memory address range 12. If a memory transaction 2B initiated on primary bus 4 does not fall within address range 12, it is not claimed by the bridge. A memory transaction 2C initiated on secondary bus 6 of the bridge is claimed and passed through to primary bus 4 of the bridge if it falls outside range 12. If a memory transaction 2D initiated on secondary bus 6 is within memory address range 12, it is not claimed by the bridge. Under normal circumstances, the above functional characteristics are not detrimental.
However, PCI/PCIx bridges are also used in high function input-output (I/O) adapters, e.g., for use with hard drives, that may include a processor and an entire computer subsystem implemented on the secondary bus of the bridge. In these settings, it is desirable to maintain a separation of resources that conventional transparent PCI/PCIx bridges are incapable of providing. The separation of resources is advantageous, for example, because the computer subsystem used in the aforementioned high function I/O adapter setting may require a large but sparsely populated memory range. Furthermore, it is often convenient or desirable to “hard wire” the memory addresses of memory mapped I/O devices and resources within the computer subsystem contained on the high function I/O adapter. This function is impossible with conventional transparent PCI/PCIx bridges.
Another problem arises relative to storage networking I/O adapters, which typically use an architecture where the I/O devices are hidden from the host operating system (OS) and basic input-output system (BIOS). As a result, the computer subsystem thereon must claim additional memory resources from the host for these devices. Due to the accelerated growth of I/O subsystems, host memory resources are becoming increasingly overburdened. The coexistence of many of these adapters within the same computer system is therefore difficult or impossible without some method to circumvent the sharing of a single memory address space by the host and all the attached I/O devices.
In view of the foregoing, there is a need in the art for a PCI bridge for an I/O adapter that provides transparent PCI/PCIx bridge functionality, but also allows for separation of memory resources.